An ever increasing demand for more compact and faster integrated circuits has led to the design of various integrated circuit chip and substrate assemblies. One such chip and substrate assembly is disclosed in U.S. Pat. No. 4,670,770 issued to TAI on June 2, 1987 and entitled INTEGRATED CIRCUIT CHIP-AND-SUBSTRATE ASSEMBLY. The TAI Patent discloses an integrated circuit assembly which can be disposed within a well formed in a silicon substrate. The integrated circuit and well have complimentary beveled edges, preferably formed by anisotropic etching. The integrated circuit assembly is electrically connected to the well via conductive conduits formed upon the beveled edges of the integrated circuit and the well.
Conductive conduits can be formed upon the surface of the substrate to interconnect a plurality of integrated circuits and also to permit the interconnection of various integrated circuits and discrete components. Thus, compared to contemporarily packaged integrated circuit chips, e.g., DIP (dual in-line pin), SIP (single in-line pin) and PGA (pin grid array), disposed upon contemporary printed circuit boards, comparatively high circuit density and speed is achieved.
The use of a single layer substrate as disclosed by TAI limits the number of traces electrically connecting the integrated circuit to the substrate. The number of traces is limited to the fixed number of conductive conduits that can be formed upon the surface of the substrate without making each conductive conduit too thin to efficiently conduct or making the space between conduits so small that adjacent conduits react capacitively. The number of circuits that can be formed upon the integrated circuit chip is limited by the ability to connect those circuits to the substrate. Therefore, the number of circuits that can be formed upon the integrated circuit chip, and consequently the overall circuit density, is strictly limited by the ability to interconnect integrated circuits and to connect those circuits to external circuitry.
Although such integrated circuit chip and substrate assemblies have proven generally suitable for their intended purposes, they possess inherent deficiencies which detract from their overall effectiveness in the marketplace. Improvements in circuit density and speed are necessitated by the continuous technological advances which strive to obtain more functions and functions of greater complexity from smaller packages. In view of the shortcomings of the prior art, it is desirable to provide a means for increasing the number and density of conductive conduits which may interconnect integrated circuits and connect those integrated circuits to external circuitry.
As such, although the prior art has recognized to a limited extent the problem of increasing the density of integrated circuit chip and substrate assemblies, the proposed solutions have to date been ineffective in providing a satisfactory remedy.